1. Field of the Invention
This invention relates to the compensation of transmission losses in signals received by a receiver circuit.
2. Description of the Related Art
High speed automatic test equipment (ATE) systems have sufficiently high receive bandwidth that nonidealities in the transmission medium between the device under test (DUT) and the ATE pin electronics often contribute a significant limitation to overall system performance. This transmission medium, or path, generally comprises several cables, connectors, printed circuit board traces and “pogo pins” that ultimately make contact with the DUT. The losses associated with such components primarily manifest as the “skin effect”, in which the resistance seen by the propagating signal becomes an increasing function of frequency. Because every signal can be represented by a superposition of many frequency components, certain components of the signal suffer greater loss than others, thus producing a dispersive effect that degrades the received signal. If the original signal is to be presented to the pin electronics with minimal distortion, great care must be taken in the design of the transmission path. In many cases, however, the frequency components present in very high speed signals are so high that even the best quality transmission path can cause significant degradation in the signal integrity. In such cases the pin electronics receiver, typically a comparator, can provide special circuitry to compensate for the expected transmission losses. Such circuitry is often included as a part of the pin electronics comparator, and is generally referred to as cable loss compensation.
A typical ATE setup is illustrated in simplified form in FIG. 1. A pattern generator 2 controls the operation of a driver 4, which transmits test signal pulses through a transmission medium 6 to a DUT 8.
As illustrated, the test signal is applied to a DUT input pin 10, with the DUT response taken from an output pin 12 and transmitted via another transmission medium 14 to a comparator 16, where it is compared with a threshold reference voltage supplied by a reference voltage generator 18 that is typically programmable. Instead of applying the test signal to a DUT input pin and taking the DUT response from a separate pin, both transmission media could be connected to a single DUT input/output pin. The DUT will typically include hundreds of pins, some of which can be input, others output, and the remainder input/output. The comparator 16 produces a differential output that indicates whether the input voltage Vin from the DUT exceeds or is less than the threshold reference voltage Vref.
FIG. 2 illustrates in simplified form a commonly implemented comparator input stage using bipolar process technology. Vin is the dynamic signal received from the DUT, while Vref is the static reference against which it is compared. The input stage includes a voltage-to-current converter (VTC), implemented as a transconductance amplifier 20, which provides an output to a current-to-voltage converter (CTV), implemented as a transimpedance amplifier 22. The transimpedance amplifier in turn produces an output to drive the comparator's second stage, which may be similar in design to the first stage.
In this illustration, the transconductance amplifier 20 includes a pair of npn transistors. Q1 and Q2 connected respectively in input and reference branches, with a current source I0 connected to the emitters of both transistors to draw current through them, and current sources I1 and I2 supplying currents to the collectors of Q1 and Q2, respectively. I1 and I2 are both nominally equal to a value greater than IO/2. The input voltage Vin is applied to the base of a buffer npn transistor Q3, the emitter of which is connected to the base of Q1, while the reference voltage Vref is connected to the base of an npn buffer transistor Q4, the emitter of which is connected to the base of Q2. Differential amplifier outputs are taken along lines 24 and 26 from the collectors of Q1 and Q2, respectively.
When Vin is less than Vref, a greater current will flow through Q2 than through Q1. The current on transconductance output line 24, which is equal to (I1−IQ1), will accordingly be greater than the current on output line 26, which is equal to (I2−IQ2). Conversely, when Vin exceeds Vref the portion of I1 diverted to output line 24 will be less than the portion of I2 diverted to output line 26. The voltage differential between Vin and Vref is thus converted to a current differential between lines 24 and 26.
Transimpedance amplifier 22 is implemented with a pair of pnp transistors Q5 and Q6 which have their bases connected in common to a bias level Vb, their emitters connected respectively to lines 24 and 26, and their collectors connected respectively to load resistors Rl5 and Rl6. The transimpedance amplifier's differential output is taken from the collectors of Q5 and Q6 and supplied to the comparator's second stage.
In available pin electronics circuitry, cable loss compensation has been implemented by adding a first order peaking response to the comparator input stage. The common method is to differentiate the input signal, and superimpose the result onto the threshold (reference) input. In the circuit of FIG. 2, this is accomplished by modulating the ordinarily static Vref input so as to pre-distort the apparent threshold in such a way as to compensate for degradations in the dynamic Vin signal.
This concept is illustrated in FIGS. 3 and 4. FIG. 3 illustrates the ideal case, in which Vin rises rapidly and linearly from a low state well below Vref to a high state above Vref, and maintains this level for the duration of the pulse. Recognition of the leading edge is triggered by Vin exceeding Vref.
FIG. 4 illustrates a more practical case when unavoidable cable losses are considered. The rising edge slope of Vin gradually tapers towards its upper end, rather than continuing linearly to a maximum value as in FIG. 3. This can be approximately compensated by reducing Vref by an amount proportional to the slope of Vin. Thus, when Vin begins to rise linearly, Vref decreases linearly from its maximum value maxVref. This continues until the slope of Vin begins to taper, at which point Vref reaches its minimum value minVref and then gradually rises back to maxVref as the slope of Vin approaches zero. Due to the dip in Vref, the effect of the nonlinear Vin slope is approximately compensated. Because the input differential (Vin−Vref) in FIGS. 3 and 4 is identical, the comparator output response would be the same in both cases, thus compensating for the distortion imposed upon the signal by the nonideal transmission path.
FIG. 5 illustrates a pair of complementary currents Ip and In that are generated to implement the compensation. Ip abruptly increases from Ipk/2 and then gradually tapers back to Ipk/2 along an exponential path 28, while In abruptly decreases from Ipk/2 and then gradually increases along exponential path 30 back up to Ipk/2. To the extent that the cable loss characteristics can be represented by a single pole time constant response such as in FIG. 5, these currents can be applied to the reference input of a comparator to produce the desired compensation response. In general, cable loss effects are multi-order, and a single-order scheme can provide only an approximate compensation.
FIG. 6 illustrates a circuit that has been used to differentiate the input signal to provide the complementary currents Ip and In. This is only one of several designs that could be used. A pair of npn bipolar transistors Q7 and Q8 are differentially connected, with the base of Q7 connected through a resistor R1 to Vin, the bases of Q7 and Q8 connected to each other through a resistor R2, and the base of Q8 connected to a fixed voltage level (such as ground) through a capacitor C1. A current source Ipk is connected to the emitters of Q7 and Q8 to draw current through the transistors, with the collector currents of Q7 and Q8 establishing Ip and In, respectively.
Before the arrival of a Vin pulse, Q7 and Q8 are equally biased, causing Ip and In to share the current Ipk equally, with respective values of Ipk/2. When a Vin pulse first arrives, C1 appears as a short circuit or very low impedance, allowing a current to flow through the RC circuit to increase the base bias of Q7, but not Q8. This diverts a portion of the Ipk current from Q8 to Q7, causing Ip to abruptly rise and In to abruptly fall. As C1 charges up with an exponential characteristic, it takes more and more of the Vin voltage, gradually raising the base bias on Q8 until it equalizes with the base bias of Q7. This restores Ip and In to equality with Ipk/2 along the paths 28 and 30 of FIG. 5.
The correction currents Ip and In are generally applied to the comparator reference input using a technique such as that illustrated in FIG. 7. A resistor R3 is connected to the base of Q4 at the input side of the comparator. Ip and In are then imposed across R3 to produce the voltage compensation. A disadvantage of this method is that a resistor inserted at this point in the circuit causes a destabilizing effect, and its resistance must therefore be kept relatively small. This implies that the Ip and In currents must be made correspondingly large to generate a corrective signal of sufficient amplitude.
To overcome this limitation, the Ip and In currents are AC coupled to opposite ends of R3 through respective capacitors C2 and C3. If the capacitor on the input side of the emitter follower Q4 is sufficiently large, it can re-stabilize the follower despite the presence of the resistor. However, it is still necessary to provide a relatively large resistor to prevent Ip and In from becoming excessive. As an example, assume that a 4V signal is to be applied at the comparator input, and a requirement exists for a 20% peaking amplitude. It is therefore necessary to impose a compensating signal of 0.8V (20% of 4V) on the reference input. If resistor R3 is made to be 200 Ohm, then Ip and In must have magnitudes of approximately +/−4 mA. This requires substantial power dissipation. Furthermore, the RC time constant formed by the resistor and the coupling capacitors can interfere with the desired time constant of Ip and In. For these reasons, it is very difficult to use this method for anything other than a simple first order cable loss compensation scheme.
While the above description is for ATE circuits, similar problems exist with other receiver circuits for differential signals, such as differential line receivers for clock or data recovery circuits, and telecommunication input circuits.